Multiplication is a common operation in many applications and there exist various types of multiplication operations. Current\nhigh level synthesis (HLS) flows generally treat all multiplication operations equally and indistinguishable from each other\nleading to inefficient mapping to resources. This paper proposes algorithms for automatically identifying the different types of\nmultiplication operations and investigates the ensemble of these different types of multiplication operations. This distinguishes it\nfrom previous works where mapping strategies for an individual type of multiplication operation have been investigated and the\ntype of multiplication operation is assumed to be known a priori. A new cost model, independent of device and synthesis tools, for\nestablishing priority among different types of multiplication operations for mapping to on-chip DSP blocks is also proposed.This\ncost model is used by a proposed analysis and priority ordering based mapping strategy targeted at making efficient use of hard\nDSP blocks on FPGAs while maximizing the operating frequency of designs. Results show that the proposed methodology could\nresult in designs which were at least 2Ã?â?? faster in performance than those generated by commercial HLS tool: Vivado-HLS.
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